Conventional memory circuits which utilize static memory cells, such circuits including static random access memories (SRAMs), FIFOs, dual-port memories, and microprocessors and other logic devices with such memory embedded therein, are generally organized in rows and columns. In these conventional memories, a row select line, generally decoded from a row address value, connects each of a number of memory cells associated with the row address value to a pair of bit lines; each pair of bit lines are associated with a column of memory cells. During a read operation, the bit line pair communicates, to a sense amplifier or other output circuitry, a differential signal corresponding to the data state stored in the memory cell in its associated column which is also in the selected row. Conversely, during a write operation, the bit line pair communicates a differential signal from input circuitry to the memory cell in its associated column which is in the selected row.
An important factor in the performance of a particular memory circuit is the speed at which such read and write operations can be reliably performed. The reliability of such operations is improved where the differential signal communicated by the bit lines is as large as possible. For a read operation, the sense amplifier or other circuit can more accurately read the data state where the differential voltage between the bit lines is large. Especially where the memory cells are fabricated conventionally as cross-coupled inverters with resistive loads (the value of the resistors in the loads being as high as possible, for example on the order of Teraohms), noise immunity of the cell is improved by presentation of a large differential voltage on the bit lines during the write operation. Accordingly, the voltage swing of the bit lines in such memories is preferably as large as possible, occurring in as short a time as possible.
Conventional techniques for controlling the bit lines of such memory circuits to quickly accomplish voltage swings thereon include the precharging and equilibration (also referred to as equalization) of each bit line pair to a known voltage prior to each operation. The precharging and equilibration in such conventional techniques is performed by a clocked signal, which causes the precharge and equilibration for all bit lines at the same time, as described in Minato, et al., "A 20 ns 64K CMOS SRAM", Digest of Technical Papers, 1984 IEEE International Solid-State Circuits Conference (IEEE, 1984), pp. 222-23. In this way, the bit lines will not have to make a full transition from one differential state to the other in successive cycles, significantly improving the performance of the circuit. Conventionally, the bit lines are precharged to a high voltage, such as the V.sub.cc supply, and a transistor connected between the two bit lines in each pair is turned on to equilibrate the two bit lines, ensuring that they are precharged to the same voltage.
For a read operation in a static memory circuit as described hereinabove, it is desirable to precharge and equilibrate the bit lines to V.sub.cc, and then release the bit lines to respond to the memory cell in the selected row. The memory cell in the selected row will present a differential signal on the bit lines in the bit line pair, to communicate its stored data state. Release of the bit lines after precharge and equilibration allows the selected memory cell to establish this differential voltage without opposition from the precharge and equilibration of the bit lines. A conventional write operation is performed by a write circuit discharging one of the precharged bit lines in the bit line pair to ground. This is also preferably done after release of the precharge and equilibration of the bit lines, so that the write circuit also does not have to discharge a bit line in opposition to a static load attempting to pull the discharging bit line toward the precharge voltage.
However, it is desired that bit lines in unselected columns not be allowed to float, since a memory cell in each of the unselected columns is connected thereto by operation of the word line. If the bit lines in unselected columns are left to float, in sufficiently long memory cycles (e.g., on the order of 200 nsec), unselected floating bit lines would eventually discharge to ground. During the next cycle after these bit lines are discharged, one of the bit lines in each pair (or both, if the memory precharges bit lines high) is pulled up to a voltage near V.sub.cc in a read operation. This charging of the bit lines for all unselected columns in a block, or in the entire memory, requires significant current, resulting in increased power dissipation and increased noise effects.
A first prior method for addressing this problem is to provide pull-up devices, such as static or active loads, on the bit lines. Such loads will, of course, keep unselected bit lines from floating. However, the effect of such loads on the bit lines must be overcome in both the read and write operations, which slows the performance of the memory.
Another prior method prevents the discharging of unselected floating bit lines by way of a "time-out" of the write operation. This time-out precharges and equilibrates the bit lines after the expiration of a delay time after data has been received in combination with a write enable signal, ensuring proper bit line precharge and equilibration prior to the next operation. However, in the event of a long write cycle, transitions may appear at the data inputs sufficiently often to prevent the time-out period from elapsing. In this case, unselected bit lines which are left floating would have sufficient time to discharge to ground, resulting in the large current spike during the next memory cycle.
A prior memory arrangement has included static load devices in parallel with precharge transistor which are controlled by the column decoder. Such an arrangement is illustrated in FIG. 11, where complementary bit lines BL and BL.sub.-- serve a column of memory cells in an array. Each of bit lines BL and BL.sub.-- are connected to input/output lines I/O and I/O.sub.--, respectively via pass gates PG and PG.sub.--, respectively. Pass gates PG and PG.sub.-- each consist of parallel n-channel and p-channel transistors; the gates of the p-channel transistors in pass gates PG and PG.sub.-- for a particular column are connected to line SEL from the column decode, and the gates of the n-channel transistors in pass gates PG and PG.sub.-- are connected to line SEL from the column decode, after inversion. Further according to this conventional arrangement, a p-channel equilibration transistor EQX has its source-to-drain path connected between bit lines BL and BL.sub.--, and has its gate driven by an equilibration signal EQ.sub.-- generated by timing control circuitry; line EQ.sub.-- is generated in common for all columns in the same block or sub-array.
Also in this conventional arrangement, p-channel precharge transistors PC and PC.sub.-- have their source-drain paths connected between bit lines BL and BL.sub.-- and V.sub.cc, and each have their gates connected to inverted line SEL from the column decode. Static load devices L and L.sub.-- are also used in this embodiment, each being a small (relative to precharge transistors PC and PC.sub.--) p-channel transistor having its source-drain path connected between its associated bit line and V.sub.cc, and having its gate tied low.
Accordingly, in this conventional arrangement, each of the bit lines BL and BL.sub.-- are precharged to V.sub.cc when not selected by the column decode, but have a static pull-up load applied thereto at all times. While this arrangement prevents bit lines BL and BL.sub.-- from floating when not selected, equilibration is done by a common signal (EQ.sub.--). As a result, the bit lines BL and BL.sub.-- may still develop a differential voltage when unselected, as a memory cell will be connected thereto by the selected word line. In addition, the static loads cause static power to be dissipated, and also oppose the development of a differential signal on the bit lines in a read operation, and oppose the input data driven by the write drivers in a write operation.
The control of equilibration in a memory by the column decoder, and based on the column address, is described in Tran, et al., "An 8-ns 256K ECL SRAM with CMOS Memory Array and Battery Backup Capability", J. Solid State Circuits, Vol. 23, No. 5 (IEEE, October 1988), pp. 1041-47. The memory described in this paper, while providing an equilibration device controlled by the column select line (see FIGS. 3 and 5, and the accompanying description), also utilizes bit line pull-up transistors and resistors which serve as loads during read operations, pulling the bit lines to a voltage approximately V.sub.cc -V.sub.be ; these pull-ups are also controlled during write operations according to the input data, so that the pull-up transistor is turned off for the bit line being pulled down in the write operation. In this described memory, however, in a read operation the differential voltage on the bit lines must be established by the memory cell in opposition to the load of the bipolar transistors and resistors. Furthermore, the control of the bit lines during a write operation is quite complex, as the input data must be communicated to both ends of the column.
It is therefore an object of this invention to provide a circuit which maintains precharge and equilibration of the bit lines in unselected columns of a memory.
It is a further object of this invention to provide such a circuit which allows for an architecture without static loads on the bit lines.
It is a further object of this invention to provide such a circuit which also results in reduced active power dissipation.
It is a further object of this invention to provide such a circuit which allows for efficient disabling of a column when a redundant column is enabled, and such that shorting of the replaced column to a power supply voltage will not cause DC power dissipation.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.